This invention relates generally to ferroelectric memories. More particularly, the present invention relates to a polarization method for minimizing the adverse effects of hydrogen damage to the electrical properties of thin film ferroelectric capacitors and memories.
Ferroelectric materials are used in storage node capacitors due to their electrical properties of retention, read/write endurance, and speed of the write cycle. In a typical implementation, a ferroelectric capacitor "stack" includes a platinum or iridium bottom electrode, a ferroelectric dielectric layer, and a platinum or iridium top electrode. The ferroelectric capacitor stack is then inserted into a conventional CMOS process flow with some minor modifications of the masking layers.
Referring now to FIG. 9 a hysteresis loop 38 is shown, which illustrates the electrical properties of a ferroelectric capacitor used in a Hysteresis loop 38 is centered about the origin of a charge (Q)--voltage (-V, +V) graph, wherein voltage is plotted along the X-axis, and charge is plotted along the Y-axis. A ferroelectric capacitor has two stable states that can be used for data storage. These are shown as operating points 1 and 3 on hysteresis loop 38. These points represent more or less permanent stable states inside the ferroelectric material that are retained after an externally applied electrical field is removed. The act of applying an external field to a ferroelectric material or capacitor is known in the art as "poling" and is described in the seminal text on ferroelectrics entitled "Piezoelectric Ceramics" by Jaffe, Cook, and Jaffe, published in 1971. On page 1 of the text, the authors state that "[t]oday we know that the polarity needed to impart piezoelectric properties can be given to an originally isotropic polycrystalline ceramic, more or less permanently, by temporary application of a strong electric field. This process, call `poling`, is analogous to the magnetizing of a permanent magnet."
Various charge components of hysteresis curve 38 have been identified in characterizing electrical performance of ferroelectric capacitors. A "P" charge component is defined as the charge associated with the application of an external positive voltage, and an excursion from operating point 1 to operating point 2 on hysteresis curve 38. A "U" charge component is defined as the charge associated with the application of an external positive voltage, and an excursion from operating point 3 to operating point 2 on hysteresis curve 38. An "N" charge component is defined as the charge associated with the application of an external negative voltage, and an excursion from operating point 3 to operating point 4 on hysteresis curve 38. A "D" charge component is defined as the charge associated with the application of an external negative voltage, and an excursion from operating point 1 to operating point 4 on hysteresis curve 38.
Hysteresis curve 38 is generated using the "Sawyer-Tower" circuit 40 shown in FIG. 10. This circuit is well known in the ferroelectric art and is exceedingly simple in construction and operation. The basic components of this circuit are an input voltage or pulse generator, designated "Vin" in FIG. 10, a ferroelectric capacitor under test CF, a linear load capacitor CL, and an output pin 42. The output pin 42 is monitored by a voltmeter or oscilloscope [not shown in FIG. 10] as required. In order to make charge measurements and to generate a hysteresis curve, the capacitance of the load capacitor CL must be made much greater than the capacitance of the ferroelectric capacitor CF under test. In this way, most of the input voltage will be dropped across the capacitor under test The output voltage, however, can be related to the charge liberated by the ferroelectric capacitor under test using the well-known charge equation Q=CV, wherein "C" is equal to CL.
The operation of the "Sawyer-Tower" circuit and corresponding hysteresis loop is further explained at pages 37-38 of the Jaffe, Cook, and Jaffe text referred to above. "The commonly accepted criterion of ferroelectricity is a hysteresis loop on a D-E display. This is usually done with a cathode-ray oscillograph. [footnote omitted] Briefly, the method consists of applying an alternating voltage and relating the stored charge to the instantaneous voltage. [figure similar to FIG. 10 omitted] A large integrating capacitor is placed in series with the sample. The voltage across it measures the charge stored on the test sample and is conventionally displayed as the vertical deflection of an oscillograph. The applied voltage is displayed as the horizontal deflection."
For testing multiple capacitors, test circuit 40 can of course be used seriatim. Also, multiple load capacitors and output ports can also be used as desired. The basic technique for measuring the charge remains the same.
A portion of a one-transistor, one-capacitor ("1T/1C") ferroelectric memory array 44 is shown in FIG. 11. While only four individual memory cells are depicted, it is known by those skilled in the art that the array can be extended both in the number of columns and number of rows as required. Each 1T/1C memory cell includes a pass transistor 46 and an associated ferroelectric storage capacitor 48. Each row of memory cells includes a word line (WL1, WL2) coupled to the gate of each pass transistor 46, and a plate line (PL1, PL2) coupled to ferroelectric capacitors 48. Each column of memory cells includes a bit line (BL1, BL2) coupled to a source/drain of the each pass transistor 46, which is in turn coupled to a sense amplifier (not shown in FIG. 11). A reference cell is also coupled to the sense amplifier in a 1T/1C design, which can be simply another 1T/1C memory cell. To establish a reference level, the value of the capacitor in the cell is sometimes adjusted. More complicated circuits, however, can be used to establish a stable reference level.
The memory array 44 shown in FIG. 11 is manufactured in an integrated circuit including conventional CMOS circuitry. During the manufacturing process, the integrated circuit can be exposed to hydrogen from numerous sources. Hydrogen can attack the PZT material (lead zirconate titanate) that is typically used in integrated ferroelectric capacitors and degrade electrical performance. An otherwise desirable hydrogen-containing "forming gas" anneal, which is typically done on CMOS circuitry is usually omitted in the manufacture of ferroelectric memories to avoid "line degradation" or loss of electrical performance during manufacturing. Once the integrated circuit is manufactured and tested, further hydrogen exposure and electrical performance degradation is possible in the subsequent packaging process, especially if plastic packaging is used.
Perhaps the biggest challenge, therefore, is preventing the reduction of the oxide-based ferroelectric film during exposure to a hydrogen containing ambient and/or films during processing subsequent to the ferroelectric deposition.
What is desired, therefore, is a method compatible with existing ferroelectric memory manufacturing methods that will minimize hydrogen damage during both integrated circuit manufacture and packaging, and may even allow a forming gas anneal during integrated circuit manufacturing.